;	DDN Research [http://ddn.at.ua/]
;	DiAVR Generated Assembler Listing
;	Date: 03-21-2015 || Time: 22:36:21
;	Search File: D:\\\avr\atmega8l.HEX
;	 
;	 
0x0:		nop		;No operation
0x2:		nop		;No operation
0x4:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x6:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x8:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0xA:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0xC:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0xE:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0xA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0xA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0xA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0xAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0xAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0xAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0xB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0xB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0xB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0xB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0xB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0xBA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0xBC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0xBE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0xC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0xC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xD0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xD2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xD4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xD6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xD8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xDA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xDC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xDE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x100:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x102:		ld r8, Z	 ;Load Indirect  
0x104:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x106:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x108:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x10A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x10C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x10E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x110:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x112:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x114:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x116:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x118:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x11A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x11C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x11E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x120:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x122:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x126:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x128:		;Unknown command CODE: 0x9393
0x12A:		;Unknown command CODE: 0x9494
0x12C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x12E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x130:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x132:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x134:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x136:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x138:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x13A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x13C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x13E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x140:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x142:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x144:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x146:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x148:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x14A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x14C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x14E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x150:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x152:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x154:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x156:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x158:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x15A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x15C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x15E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x160:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x162:		in r11,  0x0	 ;In Port Rd<-P
0x164:		in r27,  0x1	 ;In Port Rd<-P
0x166:		in r11,  0x12	 ;In Port Rd<-P
0x168:		in r27,  0x13	 ;In Port Rd<-P
0x16A:		in r11,  0x24	 ;In Port Rd<-P
0x16C:		in r27,  0x25	 ;In Port Rd<-P
0x16E:		in r11,  0x36	 ;In Port Rd<-P
0x170:		in r27,  0x37	 ;In Port Rd<-P
0x172:		out  0x8, r11	 ;Out Port    P<-Rr
0x174:		out  0x9, r27	 ;Out Port    P<-Rr
0x176:		out  0x1A, r11	 ;Out Port    P<-Rr
0x178:		out  0x1B, r27	 ;Out Port    P<-Rr
0x17A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x17C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x17E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x180:		out  0x3F, r27	 ;Out Port    P<-Rr
0x182:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x304  
0x184:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x508  
0x186:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x70C  
0x188:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x910  
0x18A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0xB14  
0x18C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0xD18  
0x18E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0xF1C  
0x190:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1120  
0x192:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF324  
0x194:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF528  
0x196:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF72C  
0x198:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF930  
0x19A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFB34  
0x19C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFD38  
0x19E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF3C  
0x1A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x140  
0x1A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x344  
0x1A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x548  
0x1A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x74C  
0x1A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x950  
0x1AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0xB54  
0x1AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0xD58  
0x1AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0xF5C  
0x1B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1160  
0x1B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFF364  
0x1B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xFFFFF568  
0x1B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xFFFFF76C  
0x1B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xFFFFF970  
0x1BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0xFFFFFB74  
0x1BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0xFFFFFD78  
0x1BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0xFFFFFF7C  
0x1C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x180  
0x1C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x1C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x1C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x1C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x1CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x1CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x1CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x1D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x1D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x1D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x1D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x1D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x1DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x1DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x1DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x1E0:		ser r30		 ;Set Register    Rd<-$FF
0x1E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x220
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x1E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x262
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x1E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x1A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x1E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x1E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x1EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x228
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x1EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x26A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x1EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x1AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x1F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x1EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x1F2:		;Unknown command CODE: 0xF8F8
0x1F4:		;Unknown command CODE: 0xF9F9
0x1F6:		;Unknown command CODE: 0xFAFA
0x1F8:		;Unknown command CODE: 0xFBFB
0x1FA:		;Unknown command CODE: 0xFCFC
0x1FC:		;Unknown command CODE: 0xFDFD
0x1FE:		;Unknown command CODE: 0xFEFE
0x200:		;Unknown command CODE: 0xFFFF
0x202:		nop		;No operation
0x204:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x206:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x208:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x20A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x20C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x20E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x210:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x212:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x214:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x216:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x218:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x21A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x21C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x21E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x220:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x222:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x224:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x226:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x228:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x22A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x22C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x22E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x230:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x232:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x234:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x236:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x238:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x23A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x23C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x23E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x240:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x242:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x244:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x246:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x248:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x24A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x24C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x24E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x250:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x252:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x254:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x256:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x258:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x25A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x25C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x25E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x260:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x262:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x264:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x266:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x268:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x26A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x26C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x26E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x270:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x272:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x274:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x276:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x278:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x27A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x27C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x27E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x280:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x282:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x284:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x286:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x288:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x28A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x28C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x28E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x290:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x292:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x294:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x296:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x298:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x29A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x29C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x29E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x2A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x2A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x2A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x2A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x2A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x2AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x2AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x2AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x2B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x2B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x2B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x2B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x2B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x2BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x2BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x2BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x2C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x2C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x2E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x2FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x300:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x302:		ld r8, Z	 ;Load Indirect  
0x304:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x306:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x308:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x30A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x30C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x30E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x310:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x312:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x314:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x316:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x318:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x31A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x31C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x31E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x320:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x322:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x326:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x328:		;Unknown command CODE: 0x9393
0x32A:		;Unknown command CODE: 0x9494
0x32C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x32E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x330:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x332:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x334:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x336:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x338:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x33A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x33C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x33E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x340:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x342:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x344:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x346:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x348:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x34A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x34C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x34E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x350:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x352:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x354:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x356:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x358:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x35A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x35C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x35E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x360:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x362:		in r11,  0x0	 ;In Port Rd<-P
0x364:		in r27,  0x1	 ;In Port Rd<-P
0x366:		in r11,  0x12	 ;In Port Rd<-P
0x368:		in r27,  0x13	 ;In Port Rd<-P
0x36A:		in r11,  0x24	 ;In Port Rd<-P
0x36C:		in r27,  0x25	 ;In Port Rd<-P
0x36E:		in r11,  0x36	 ;In Port Rd<-P
0x370:		in r27,  0x37	 ;In Port Rd<-P
0x372:		out  0x8, r11	 ;Out Port    P<-Rr
0x374:		out  0x9, r27	 ;Out Port    P<-Rr
0x376:		out  0x1A, r11	 ;Out Port    P<-Rr
0x378:		out  0x1B, r27	 ;Out Port    P<-Rr
0x37A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x37C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x37E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x380:		out  0x3F, r27	 ;Out Port    P<-Rr
0x382:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x504  
0x384:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x708  
0x386:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x90C  
0x388:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0xB10  
0x38A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0xD14  
0x38C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0xF18  
0x38E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x111C  
0x390:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1320  
0x392:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF524  
0x394:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF728  
0x396:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF92C  
0x398:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFB30  
0x39A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFD34  
0x39C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF38  
0x39E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x13C  
0x3A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x340  
0x3A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x544  
0x3A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x748  
0x3A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x94C  
0x3A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0xB50  
0x3AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0xD54  
0x3AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0xF58  
0x3AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x115C  
0x3B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1360  
0x3B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFF564  
0x3B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xFFFFF768  
0x3B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xFFFFF96C  
0x3B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xFFFFFB70  
0x3BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0xFFFFFD74  
0x3BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0xFFFFFF78  
0x3BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x17C  
0x3C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x380  
0x3C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x3C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x3C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x3C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x3CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x3CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x3CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x3D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x3D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x3D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x3D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x3D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x3DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x3DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x3DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x3E0:		ser r30		 ;Set Register    Rd<-$FF
0x3E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x420
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x3E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x462
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x3E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x3A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x3E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x3E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x3EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x428
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x3EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x46A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x3EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x3AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x3F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x3EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x3F2:		;Unknown command CODE: 0xF8F8
0x3F4:		;Unknown command CODE: 0xF9F9
0x3F6:		;Unknown command CODE: 0xFAFA
0x3F8:		;Unknown command CODE: 0xFBFB
0x3FA:		;Unknown command CODE: 0xFCFC
0x3FC:		;Unknown command CODE: 0xFDFD
0x3FE:		;Unknown command CODE: 0xFEFE
0x400:		;Unknown command CODE: 0xFFFF
0x402:		nop		;No operation
0x404:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x406:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x408:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x40A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x40C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x40E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x410:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x412:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x414:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x416:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x418:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x41A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x41C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x41E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x420:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x422:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x424:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x426:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x428:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x42A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x42C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x42E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x430:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x432:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x434:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x436:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x438:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x43A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x43C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x43E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x440:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x442:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x444:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x446:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x448:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x44A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x44C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x44E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x450:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x452:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x454:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x456:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x458:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x45A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x45C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x45E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x460:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x462:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x464:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x466:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x468:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x46A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x46C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x46E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x470:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x472:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x474:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x476:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x478:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x47A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x47C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x47E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x480:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x482:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x484:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x486:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x488:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x48A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x48C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x48E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x490:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x492:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x494:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x496:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x498:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x49A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x49C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x49E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x4A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x4A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x4A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x4A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x4A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x4AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x4AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x4AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x4B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x4B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x4B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x4B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x4B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x4BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x4BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x4BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x4C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x4C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x4E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x4FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x500:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x502:		ld r8, Z	 ;Load Indirect  
0x504:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x506:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x508:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x50A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x50C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x50E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x510:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x512:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x514:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x516:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x518:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x51A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x51C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x51E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x520:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x522:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x526:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x528:		;Unknown command CODE: 0x9393
0x52A:		;Unknown command CODE: 0x9494
0x52C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x52E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x530:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x532:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x534:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x536:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x538:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x53A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x53C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x53E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x540:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x542:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x544:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x546:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x548:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x54A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x54C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x54E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x550:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x552:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x554:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x556:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x558:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x55A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x55C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x55E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x560:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x562:		in r11,  0x0	 ;In Port Rd<-P
0x564:		in r27,  0x1	 ;In Port Rd<-P
0x566:		in r11,  0x12	 ;In Port Rd<-P
0x568:		in r27,  0x13	 ;In Port Rd<-P
0x56A:		in r11,  0x24	 ;In Port Rd<-P
0x56C:		in r27,  0x25	 ;In Port Rd<-P
0x56E:		in r11,  0x36	 ;In Port Rd<-P
0x570:		in r27,  0x37	 ;In Port Rd<-P
0x572:		out  0x8, r11	 ;Out Port    P<-Rr
0x574:		out  0x9, r27	 ;Out Port    P<-Rr
0x576:		out  0x1A, r11	 ;Out Port    P<-Rr
0x578:		out  0x1B, r27	 ;Out Port    P<-Rr
0x57A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x57C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x57E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x580:		out  0x3F, r27	 ;Out Port    P<-Rr
0x582:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x704  
0x584:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x908  
0x586:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0xB0C  
0x588:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0xD10  
0x58A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0xF14  
0x58C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1118  
0x58E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x131C  
0x590:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1520  
0x592:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF724  
0x594:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF928  
0x596:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFB2C  
0x598:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFD30  
0x59A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF34  
0x59C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x138  
0x59E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x33C  
0x5A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x540  
0x5A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x744  
0x5A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x948  
0x5A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0xB4C  
0x5A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0xD50  
0x5AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0xF54  
0x5AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1158  
0x5AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x135C  
0x5B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1560  
0x5B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFF764  
0x5B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xFFFFF968  
0x5B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xFFFFFB6C  
0x5B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xFFFFFD70  
0x5BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0xFFFFFF74  
0x5BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x178  
0x5BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x37C  
0x5C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x580  
0x5C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x5C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x5C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x5C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x5CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x5CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x5CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x5D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x5D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x5D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x5D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x5D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x5DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x5DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x5DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x5E0:		ser r30		 ;Set Register    Rd<-$FF
0x5E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x620
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x5E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x662
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x5E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x5A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x5E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x5E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x5EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x628
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x5EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x66A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x5EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x5AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x5F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x5EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x5F2:		;Unknown command CODE: 0xF8F8
0x5F4:		;Unknown command CODE: 0xF9F9
0x5F6:		;Unknown command CODE: 0xFAFA
0x5F8:		;Unknown command CODE: 0xFBFB
0x5FA:		;Unknown command CODE: 0xFCFC
0x5FC:		;Unknown command CODE: 0xFDFD
0x5FE:		;Unknown command CODE: 0xFEFE
0x600:		;Unknown command CODE: 0xFFFF
0x602:		nop		;No operation
0x604:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x606:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x608:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x60A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x60C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x60E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x610:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x612:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x614:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x616:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x618:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x61A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x61C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x61E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x620:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x622:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x624:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x626:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x628:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x62A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x62C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x62E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x630:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x632:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x634:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x636:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x638:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x63A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x63C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x63E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x640:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x642:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x644:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x646:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x648:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x64A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x64C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x64E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x650:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x652:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x654:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x656:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x658:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x65A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x65C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x65E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x660:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x662:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x664:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x666:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x668:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x66A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x66C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x66E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x670:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x672:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x674:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x676:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x678:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x67A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x67C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x67E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x680:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x682:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x684:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x686:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x688:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x68A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x68C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x68E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x690:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x692:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x694:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x696:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x698:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x69A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x69C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x69E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x6A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x6A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x6A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x6A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x6A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x6AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x6AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x6AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x6B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x6B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x6B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x6B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x6B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x6BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x6BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x6BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x6C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x6C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x6E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x6FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x700:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x702:		ld r8, Z	 ;Load Indirect  
0x704:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x706:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x708:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x70A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x70C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x70E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x710:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x712:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x714:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x716:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x718:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x71A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x71C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x71E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x720:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x722:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x726:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x728:		;Unknown command CODE: 0x9393
0x72A:		;Unknown command CODE: 0x9494
0x72C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x72E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x730:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x732:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x734:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x736:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x738:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x73A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x73C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x73E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x740:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x742:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x744:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x746:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x748:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x74A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x74C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x74E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x750:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x752:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x754:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x756:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x758:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x75A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x75C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x75E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x760:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x762:		in r11,  0x0	 ;In Port Rd<-P
0x764:		in r27,  0x1	 ;In Port Rd<-P
0x766:		in r11,  0x12	 ;In Port Rd<-P
0x768:		in r27,  0x13	 ;In Port Rd<-P
0x76A:		in r11,  0x24	 ;In Port Rd<-P
0x76C:		in r27,  0x25	 ;In Port Rd<-P
0x76E:		in r11,  0x36	 ;In Port Rd<-P
0x770:		in r27,  0x37	 ;In Port Rd<-P
0x772:		out  0x8, r11	 ;Out Port    P<-Rr
0x774:		out  0x9, r27	 ;Out Port    P<-Rr
0x776:		out  0x1A, r11	 ;Out Port    P<-Rr
0x778:		out  0x1B, r27	 ;Out Port    P<-Rr
0x77A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x77C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x77E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x780:		out  0x3F, r27	 ;Out Port    P<-Rr
0x782:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x904  
0x784:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0xB08  
0x786:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0xD0C  
0x788:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0xF10  
0x78A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1114  
0x78C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1318  
0x78E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x151C  
0x790:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1720  
0x792:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFF924  
0x794:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFB28  
0x796:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFD2C  
0x798:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF30  
0x79A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x134  
0x79C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x338  
0x79E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x53C  
0x7A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x740  
0x7A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x944  
0x7A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0xB48  
0x7A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0xD4C  
0x7A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0xF50  
0x7AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1154  
0x7AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1358  
0x7AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x155C  
0x7B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1760  
0x7B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFF964  
0x7B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xFFFFFB68  
0x7B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xFFFFFD6C  
0x7B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xFFFFFF70  
0x7BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x174  
0x7BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x378  
0x7BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x57C  
0x7C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x780  
0x7C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x7C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x7C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x7C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x7CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x7CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x7CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x7D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x7D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x7D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x7D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x7D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x7DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x7DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x7DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x7E0:		ser r30		 ;Set Register    Rd<-$FF
0x7E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x820
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x7E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x862
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x7E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x7A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x7E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x7E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x7EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x828
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x7EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x86A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x7EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x7AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x7F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x7EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x7F2:		;Unknown command CODE: 0xF8F8
0x7F4:		;Unknown command CODE: 0xF9F9
0x7F6:		;Unknown command CODE: 0xFAFA
0x7F8:		;Unknown command CODE: 0xFBFB
0x7FA:		;Unknown command CODE: 0xFCFC
0x7FC:		;Unknown command CODE: 0xFDFD
0x7FE:		;Unknown command CODE: 0xFEFE
0x800:		;Unknown command CODE: 0xFFFF
0x802:		nop		;No operation
0x804:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x806:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x808:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x80A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x80C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x80E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x810:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x812:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x814:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x816:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x818:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x81A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x81C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x81E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x820:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x822:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x824:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x826:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x828:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x82A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x82C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x82E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x830:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x832:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x834:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x836:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x838:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x83A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x83C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x83E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x840:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x842:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x844:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x846:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x848:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x84A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x84C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x84E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x850:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x852:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x854:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x856:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x858:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x85A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x85C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x85E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x860:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x862:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x864:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x866:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x868:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x86A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x86C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x86E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x870:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x872:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x874:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x876:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x878:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x87A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x87C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x87E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x880:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x882:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x884:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x886:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x888:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x88A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x88C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x88E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x890:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x892:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x894:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x896:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x898:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x89A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x89C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x89E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x8A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x8A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x8A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x8A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x8A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x8AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x8AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x8AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x8B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x8B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x8B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x8B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x8B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x8BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x8BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x8BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x8C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x8C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x8E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x8FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x900:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x902:		ld r8, Z	 ;Load Indirect  
0x904:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x906:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x908:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x90A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x90C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x90E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x910:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x912:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x914:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x916:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x918:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x91A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x91C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x91E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x920:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x922:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x926:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x928:		;Unknown command CODE: 0x9393
0x92A:		;Unknown command CODE: 0x9494
0x92C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x92E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x930:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x932:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x934:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x936:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x938:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x93A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x93C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x93E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x940:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x942:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x944:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x946:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x948:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x94A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x94C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x94E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x950:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x952:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x954:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x956:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x958:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x95A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x95C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x95E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x960:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x962:		in r11,  0x0	 ;In Port Rd<-P
0x964:		in r27,  0x1	 ;In Port Rd<-P
0x966:		in r11,  0x12	 ;In Port Rd<-P
0x968:		in r27,  0x13	 ;In Port Rd<-P
0x96A:		in r11,  0x24	 ;In Port Rd<-P
0x96C:		in r27,  0x25	 ;In Port Rd<-P
0x96E:		in r11,  0x36	 ;In Port Rd<-P
0x970:		in r27,  0x37	 ;In Port Rd<-P
0x972:		out  0x8, r11	 ;Out Port    P<-Rr
0x974:		out  0x9, r27	 ;Out Port    P<-Rr
0x976:		out  0x1A, r11	 ;Out Port    P<-Rr
0x978:		out  0x1B, r27	 ;Out Port    P<-Rr
0x97A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x97C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x97E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x980:		out  0x3F, r27	 ;Out Port    P<-Rr
0x982:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0xB04  
0x984:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0xD08  
0x986:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0xF0C  
0x988:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1110  
0x98A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1314  
0x98C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1518  
0x98E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x171C  
0x990:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1920  
0x992:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFB24  
0x994:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFD28  
0x996:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF2C  
0x998:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x130  
0x99A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x334  
0x99C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x538  
0x99E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x73C  
0x9A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x940  
0x9A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0xB44  
0x9A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0xD48  
0x9A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0xF4C  
0x9A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1150  
0x9AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1354  
0x9AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1558  
0x9AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x175C  
0x9B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1960  
0x9B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFFB64  
0x9B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xFFFFFD68  
0x9B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xFFFFFF6C  
0x9B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x170  
0x9BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x374  
0x9BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x578  
0x9BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x77C  
0x9C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x980  
0x9C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x9C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x9C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x9C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x9CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x9CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x9CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x9D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x9D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x9D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x9D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x9D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x9DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x9DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x9DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x9E0:		ser r30		 ;Set Register    Rd<-$FF
0x9E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xA20
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x9E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0xA62
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x9E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x9A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x9E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x9E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x9EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0xA28
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x9EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0xA6A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x9EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x9AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x9F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x9EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x9F2:		;Unknown command CODE: 0xF8F8
0x9F4:		;Unknown command CODE: 0xF9F9
0x9F6:		;Unknown command CODE: 0xFAFA
0x9F8:		;Unknown command CODE: 0xFBFB
0x9FA:		;Unknown command CODE: 0xFCFC
0x9FC:		;Unknown command CODE: 0xFDFD
0x9FE:		;Unknown command CODE: 0xFEFE
0xA00:		;Unknown command CODE: 0xFFFF
0xA02:		nop		;No operation
0xA04:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0xA06:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0xA08:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0xA0A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0xA0C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0xA0E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0xA10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0xA12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xA14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xA16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xA18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xA1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0xA1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0xA1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0xA20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0xA22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xA24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xA26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xA28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xA2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0xA34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0xA36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0xA38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0xA3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xA42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0xA44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0xA46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0xA48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0xA4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0xA4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0xA4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0xA50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0xA52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0xA54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0xA56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0xA58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0xA5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0xA5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0xA5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0xA60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0xA62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0xA64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0xA66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0xA68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0xA6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0xA6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0xA6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0xA70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0xA72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0xA74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0xA76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0xA78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0xA7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0xA7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0xA7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0xA80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0xA82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xA9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xAA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xAA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0xAA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0xAA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0xAA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0xAAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0xAAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0xAAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0xAB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0xAB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0xAB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0xAB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0xAB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0xABA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0xABC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0xABE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0xAC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0xAC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xACA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xACC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xACE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAD0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAD2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAD4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAD6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAD8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xADA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xADC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xADE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xAE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xAFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xB00:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xB02:		ld r8, Z	 ;Load Indirect  
0xB04:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0xB06:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0xB08:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0xB0A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0xB0C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0xB0E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0xB10:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0xB12:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0xB14:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0xB16:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0xB18:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0xB1A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0xB1C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0xB1E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0xB20:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0xB22:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0xB26:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0xB28:		;Unknown command CODE: 0x9393
0xB2A:		;Unknown command CODE: 0x9494
0xB2C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0xB2E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0xB30:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0xB32:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0xB34:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0xB36:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0xB38:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0xB3A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0xB3C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0xB3E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0xB40:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0xB42:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0xB44:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0xB46:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0xB48:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0xB4A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0xB4C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0xB4E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0xB50:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0xB52:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0xB54:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0xB56:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0xB58:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0xB5A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0xB5C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0xB5E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0xB60:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0xB62:		in r11,  0x0	 ;In Port Rd<-P
0xB64:		in r27,  0x1	 ;In Port Rd<-P
0xB66:		in r11,  0x12	 ;In Port Rd<-P
0xB68:		in r27,  0x13	 ;In Port Rd<-P
0xB6A:		in r11,  0x24	 ;In Port Rd<-P
0xB6C:		in r27,  0x25	 ;In Port Rd<-P
0xB6E:		in r11,  0x36	 ;In Port Rd<-P
0xB70:		in r27,  0x37	 ;In Port Rd<-P
0xB72:		out  0x8, r11	 ;Out Port    P<-Rr
0xB74:		out  0x9, r27	 ;Out Port    P<-Rr
0xB76:		out  0x1A, r11	 ;Out Port    P<-Rr
0xB78:		out  0x1B, r27	 ;Out Port    P<-Rr
0xB7A:		out  0x2C, r11	 ;Out Port    P<-Rr
0xB7C:		out  0x2D, r27	 ;Out Port    P<-Rr
0xB7E:		out  0x3E, r11	 ;Out Port    P<-Rr
0xB80:		out  0x3F, r27	 ;Out Port    P<-Rr
0xB82:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0xD04  
0xB84:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0xF08  
0xB86:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x110C  
0xB88:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1310  
0xB8A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1514  
0xB8C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1718  
0xB8E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x191C  
0xB90:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1B20  
0xB92:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFD24  
0xB94:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF28  
0xB96:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x12C  
0xB98:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x330  
0xB9A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x534  
0xB9C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x738  
0xB9E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x93C  
0xBA0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0xB40  
0xBA2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0xD44  
0xBA4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0xF48  
0xBA6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x114C  
0xBA8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1350  
0xBAA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1554  
0xBAC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1758  
0xBAE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x195C  
0xBB0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1B60  
0xBB2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFFD64  
0xBB4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xFFFFFF68  
0xBB6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x16C  
0xBB8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x370  
0xBBA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x574  
0xBBC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x778  
0xBBE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x97C  
0xBC0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0xB80  
0xBC2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0xBC4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0xBC6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0xBC8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0xBCA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0xBCC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0xBCE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0xBD0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0xBD2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0xBD4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0xBD6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0xBD8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0xBDA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0xBDC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0xBDE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0xBE0:		ser r30		 ;Set Register    Rd<-$FF
0xBE2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xC20
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0xBE4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0xC62
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0xBE6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0xBA4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0xBE8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0xBE6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0xBEA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0xC28
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0xBEC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0xC6A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0xBEE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0xBAC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0xBF0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0xBEE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0xBF2:		;Unknown command CODE: 0xF8F8
0xBF4:		;Unknown command CODE: 0xF9F9
0xBF6:		;Unknown command CODE: 0xFAFA
0xBF8:		;Unknown command CODE: 0xFBFB
0xBFA:		;Unknown command CODE: 0xFCFC
0xBFC:		;Unknown command CODE: 0xFDFD
0xBFE:		;Unknown command CODE: 0xFEFE
0xC00:		;Unknown command CODE: 0xFFFF
0xC02:		nop		;No operation
0xC04:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0xC06:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0xC08:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0xC0A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0xC0C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0xC0E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0xC10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0xC12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xC14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xC16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xC18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xC1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0xC1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0xC1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0xC20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0xC22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xC24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xC26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xC28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xC2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0xC34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0xC36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0xC38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0xC3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xC42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0xC44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0xC46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0xC48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0xC4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0xC4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0xC4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0xC50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0xC52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0xC54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0xC56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0xC58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0xC5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0xC5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0xC5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0xC60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0xC62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0xC64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0xC66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0xC68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0xC6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0xC6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0xC6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0xC70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0xC72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0xC74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0xC76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0xC78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0xC7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0xC7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0xC7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0xC80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0xC82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xC9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xCA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xCA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0xCA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0xCA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0xCA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0xCAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0xCAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0xCAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0xCB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0xCB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0xCB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0xCB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0xCB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0xCBA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0xCBC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0xCBE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0xCC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0xCC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCCA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCCC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCCE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCD0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCD2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCD4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCD6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCD8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCDA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCDC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCDE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xCE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xCFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xD00:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xD02:		ld r8, Z	 ;Load Indirect  
0xD04:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0xD06:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0xD08:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0xD0A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0xD0C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0xD0E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0xD10:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0xD12:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0xD14:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0xD16:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0xD18:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0xD1A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0xD1C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0xD1E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0xD20:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0xD22:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0xD26:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0xD28:		;Unknown command CODE: 0x9393
0xD2A:		;Unknown command CODE: 0x9494
0xD2C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0xD2E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0xD30:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0xD32:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0xD34:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0xD36:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0xD38:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0xD3A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0xD3C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0xD3E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0xD40:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0xD42:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0xD44:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0xD46:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0xD48:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0xD4A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0xD4C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0xD4E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0xD50:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0xD52:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0xD54:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0xD56:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0xD58:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0xD5A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0xD5C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0xD5E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0xD60:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0xD62:		in r11,  0x0	 ;In Port Rd<-P
0xD64:		in r27,  0x1	 ;In Port Rd<-P
0xD66:		in r11,  0x12	 ;In Port Rd<-P
0xD68:		in r27,  0x13	 ;In Port Rd<-P
0xD6A:		in r11,  0x24	 ;In Port Rd<-P
0xD6C:		in r27,  0x25	 ;In Port Rd<-P
0xD6E:		in r11,  0x36	 ;In Port Rd<-P
0xD70:		in r27,  0x37	 ;In Port Rd<-P
0xD72:		out  0x8, r11	 ;Out Port    P<-Rr
0xD74:		out  0x9, r27	 ;Out Port    P<-Rr
0xD76:		out  0x1A, r11	 ;Out Port    P<-Rr
0xD78:		out  0x1B, r27	 ;Out Port    P<-Rr
0xD7A:		out  0x2C, r11	 ;Out Port    P<-Rr
0xD7C:		out  0x2D, r27	 ;Out Port    P<-Rr
0xD7E:		out  0x3E, r11	 ;Out Port    P<-Rr
0xD80:		out  0x3F, r27	 ;Out Port    P<-Rr
0xD82:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0xF04  
0xD84:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1108  
0xD86:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x130C  
0xD88:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1510  
0xD8A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1714  
0xD8C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1918  
0xD8E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x1B1C  
0xD90:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1D20  
0xD92:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xFFFFFF24  
0xD94:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x128  
0xD96:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x32C  
0xD98:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x530  
0xD9A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x734  
0xD9C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x938  
0xD9E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0xB3C  
0xDA0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0xD40  
0xDA2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0xF44  
0xDA4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1148  
0xDA6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x134C  
0xDA8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1550  
0xDAA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1754  
0xDAC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1958  
0xDAE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x1B5C  
0xDB0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1D60  
0xDB2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xFFFFFF64  
0xDB4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x168  
0xDB6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x36C  
0xDB8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x570  
0xDBA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x774  
0xDBC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x978  
0xDBE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0xB7C  
0xDC0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0xD80  
0xDC2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0xDC4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0xDC6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0xDC8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0xDCA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0xDCC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0xDCE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0xDD0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0xDD2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0xDD4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0xDD6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0xDD8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0xDDA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0xDDC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0xDDE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0xDE0:		ser r30		 ;Set Register    Rd<-$FF
0xDE2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0xE20
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0xDE4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0xE62
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0xDE6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0xDA4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0xDE8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0xDE6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0xDEA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0xE28
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0xDEC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0xE6A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0xDEE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0xDAC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0xDF0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0xDEE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0xDF2:		;Unknown command CODE: 0xF8F8
0xDF4:		;Unknown command CODE: 0xF9F9
0xDF6:		;Unknown command CODE: 0xFAFA
0xDF8:		;Unknown command CODE: 0xFBFB
0xDFA:		;Unknown command CODE: 0xFCFC
0xDFC:		;Unknown command CODE: 0xFDFD
0xDFE:		;Unknown command CODE: 0xFEFE
0xE00:		;Unknown command CODE: 0xFFFF
0xE02:		nop		;No operation
0xE04:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0xE06:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0xE08:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0xE0A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0xE0C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0xE0E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0xE10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0xE12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xE14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xE16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xE18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0xE1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0xE1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0xE1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0xE20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0xE22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xE24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xE26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xE28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0xE2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0xE34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0xE36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0xE38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0xE3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0xE42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0xE44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0xE46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0xE48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0xE4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0xE4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0xE4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0xE50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0xE52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0xE54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0xE56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0xE58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0xE5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0xE5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0xE5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0xE60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0xE62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0xE64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0xE66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0xE68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0xE6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0xE6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0xE6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0xE70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0xE72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0xE74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0xE76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0xE78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0xE7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0xE7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0xE7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0xE80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0xE82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xE9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xEA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0xEA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0xEA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0xEA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0xEA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0xEAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0xEAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0xEAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0xEB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0xEB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0xEB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0xEB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0xEB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0xEBA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0xEBC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0xEBE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0xEC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0xEC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xECA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xECC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xECE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xED0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xED2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xED4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xED6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xED8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEDA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEDC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEDE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0xEE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xEFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF00:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0xF02:		ld r8, Z	 ;Load Indirect  
0xF04:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0xF06:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0xF08:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0xF0A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0xF0C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0xF0E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0xF10:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0xF12:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0xF14:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0xF16:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0xF18:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0xF1A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0xF1C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0xF1E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0xF20:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0xF22:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0xF26:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0xF28:		;Unknown command CODE: 0x9393
0xF2A:		;Unknown command CODE: 0x9494
0xF2C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0xF2E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0xF30:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0xF32:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0xF34:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0xF36:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0xF38:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0xF3A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0xF3C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0xF3E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0xF40:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0xF42:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0xF44:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0xF46:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0xF48:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0xF4A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0xF4C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0xF4E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0xF50:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0xF52:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0xF54:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0xF56:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0xF58:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0xF5A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0xF5C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0xF5E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0xF60:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0xF62:		in r11,  0x0	 ;In Port Rd<-P
0xF64:		in r27,  0x1	 ;In Port Rd<-P
0xF66:		in r11,  0x12	 ;In Port Rd<-P
0xF68:		in r27,  0x13	 ;In Port Rd<-P
0xF6A:		in r11,  0x24	 ;In Port Rd<-P
0xF6C:		in r27,  0x25	 ;In Port Rd<-P
0xF6E:		in r11,  0x36	 ;In Port Rd<-P
0xF70:		in r27,  0x37	 ;In Port Rd<-P
0xF72:		out  0x8, r11	 ;Out Port    P<-Rr
0xF74:		out  0x9, r27	 ;Out Port    P<-Rr
0xF76:		out  0x1A, r11	 ;Out Port    P<-Rr
0xF78:		out  0x1B, r27	 ;Out Port    P<-Rr
0xF7A:		out  0x2C, r11	 ;Out Port    P<-Rr
0xF7C:		out  0x2D, r27	 ;Out Port    P<-Rr
0xF7E:		out  0x3E, r11	 ;Out Port    P<-Rr
0xF80:		out  0x3F, r27	 ;Out Port    P<-Rr
0xF82:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1104  
0xF84:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1308  
0xF86:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x150C  
0xF88:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1710  
0xF8A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1914  
0xF8C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1B18  
0xF8E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x1D1C  
0xF90:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x1F20  
0xF92:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0x124  
0xF94:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x328  
0xF96:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x52C  
0xF98:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x730  
0xF9A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x934  
0xF9C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0xB38  
0xF9E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0xD3C  
0xFA0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0xF40  
0xFA2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1144  
0xFA4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1348  
0xFA6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x154C  
0xFA8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1750  
0xFAA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1954  
0xFAC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1B58  
0xFAE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x1D5C  
0xFB0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x1F60  
0xFB2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0x164  
0xFB4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x368  
0xFB6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x56C  
0xFB8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x770  
0xFBA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x974  
0xFBC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0xB78  
0xFBE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0xD7C  
0xFC0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0xF80  
0xFC2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0xFC4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0xFC6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0xFC8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0xFCA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0xFCC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0xFCE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0xFD0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0xFD2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0xFD4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0xFD6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0xFD8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0xFDA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0xFDC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0xFDE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0xFE0:		ser r30		 ;Set Register    Rd<-$FF
0xFE2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1020
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0xFE4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1062
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0xFE6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0xFA4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0xFE8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0xFE6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0xFEA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1028
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0xFEC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x106A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0xFEE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0xFAC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0xFF0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0xFEE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0xFF2:		;Unknown command CODE: 0xF8F8
0xFF4:		;Unknown command CODE: 0xF9F9
0xFF6:		;Unknown command CODE: 0xFAFA
0xFF8:		;Unknown command CODE: 0xFBFB
0xFFA:		;Unknown command CODE: 0xFCFC
0xFFC:		;Unknown command CODE: 0xFDFD
0xFFE:		;Unknown command CODE: 0xFEFE
0x1000:		;Unknown command CODE: 0xFFFF
0x1002:		nop		;No operation
0x1004:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1006:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1008:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x100A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x100C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x100E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1010:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1012:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1014:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1016:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1018:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x101A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x101C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x101E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1020:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1022:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1024:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1026:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1028:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x102A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x102C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x102E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1030:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1032:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1034:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1036:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1038:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x103A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x103C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x103E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1040:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1042:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1044:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1046:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1048:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x104A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x104C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x104E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1050:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1052:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1054:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1056:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1058:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x105A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x105C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x105E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1060:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1062:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1064:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1066:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1068:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x106A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x106C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x106E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1070:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1072:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1074:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1076:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1078:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x107A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x107C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x107E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1080:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1082:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1084:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1086:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1088:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x108A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x108C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x108E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1090:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1092:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1094:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1096:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1098:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x109A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x109C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x109E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x10A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x10A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x10A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x10A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x10A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x10AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x10AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x10AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x10B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x10B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x10B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x10B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x10B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x10BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x10BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x10BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x10C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x10C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x10E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x10FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1100:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1102:		ld r8, Z	 ;Load Indirect  
0x1104:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1106:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1108:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x110A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x110C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x110E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1110:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1112:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1114:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1116:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1118:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x111A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x111C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x111E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1120:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1122:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1126:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1128:		;Unknown command CODE: 0x9393
0x112A:		;Unknown command CODE: 0x9494
0x112C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x112E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1130:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1132:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1134:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1136:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1138:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x113A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x113C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x113E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1140:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1142:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1144:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1146:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1148:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x114A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x114C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x114E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1150:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1152:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1154:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1156:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1158:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x115A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x115C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x115E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1160:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1162:		in r11,  0x0	 ;In Port Rd<-P
0x1164:		in r27,  0x1	 ;In Port Rd<-P
0x1166:		in r11,  0x12	 ;In Port Rd<-P
0x1168:		in r27,  0x13	 ;In Port Rd<-P
0x116A:		in r11,  0x24	 ;In Port Rd<-P
0x116C:		in r27,  0x25	 ;In Port Rd<-P
0x116E:		in r11,  0x36	 ;In Port Rd<-P
0x1170:		in r27,  0x37	 ;In Port Rd<-P
0x1172:		out  0x8, r11	 ;Out Port    P<-Rr
0x1174:		out  0x9, r27	 ;Out Port    P<-Rr
0x1176:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1178:		out  0x1B, r27	 ;Out Port    P<-Rr
0x117A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x117C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x117E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1180:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1182:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1304  
0x1184:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1508  
0x1186:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x170C  
0x1188:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1910  
0x118A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1B14  
0x118C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1D18  
0x118E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x1F1C  
0x1190:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2120  
0x1192:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0x324  
0x1194:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x528  
0x1196:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x72C  
0x1198:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x930  
0x119A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0xB34  
0x119C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0xD38  
0x119E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0xF3C  
0x11A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1140  
0x11A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1344  
0x11A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1548  
0x11A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x174C  
0x11A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1950  
0x11AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1B54  
0x11AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1D58  
0x11AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x1F5C  
0x11B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2160  
0x11B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0x364  
0x11B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x568  
0x11B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x76C  
0x11B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x970  
0x11BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0xB74  
0x11BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0xD78  
0x11BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0xF7C  
0x11C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1180  
0x11C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x11C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x11C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x11C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x11CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x11CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x11CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x11D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x11D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x11D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x11D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x11D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x11DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x11DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x11DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x11E0:		ser r30		 ;Set Register    Rd<-$FF
0x11E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1220
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x11E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1262
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x11E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x11A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x11E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x11E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x11EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1228
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x11EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x126A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x11EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x11AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x11F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x11EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x11F2:		;Unknown command CODE: 0xF8F8
0x11F4:		;Unknown command CODE: 0xF9F9
0x11F6:		;Unknown command CODE: 0xFAFA
0x11F8:		;Unknown command CODE: 0xFBFB
0x11FA:		;Unknown command CODE: 0xFCFC
0x11FC:		;Unknown command CODE: 0xFDFD
0x11FE:		;Unknown command CODE: 0xFEFE
0x1200:		;Unknown command CODE: 0xFFFF
0x1202:		nop		;No operation
0x1204:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1206:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1208:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x120A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x120C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x120E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1210:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1212:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1214:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1216:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1218:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x121A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x121C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x121E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1220:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1222:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1224:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1226:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1228:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x122A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x122C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x122E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1230:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1232:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1234:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1236:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1238:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x123A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x123C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x123E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1240:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1242:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1244:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1246:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1248:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x124A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x124C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x124E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1250:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1252:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1254:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1256:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1258:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x125A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x125C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x125E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1260:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1262:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1264:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1266:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1268:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x126A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x126C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x126E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1270:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1272:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1274:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1276:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1278:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x127A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x127C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x127E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1280:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1282:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1284:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1286:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1288:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x128A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x128C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x128E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1290:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1292:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1294:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1296:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1298:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x129A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x129C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x129E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x12A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x12A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x12A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x12A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x12A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x12AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x12AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x12AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x12B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x12B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x12B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x12B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x12B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x12BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x12BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x12BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x12C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x12C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x12E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x12FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1300:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1302:		ld r8, Z	 ;Load Indirect  
0x1304:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1306:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1308:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x130A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x130C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x130E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1310:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1312:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1314:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1316:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1318:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x131A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x131C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x131E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1320:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1322:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1326:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1328:		;Unknown command CODE: 0x9393
0x132A:		;Unknown command CODE: 0x9494
0x132C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x132E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1330:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1332:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1334:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1336:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1338:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x133A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x133C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x133E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1340:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1342:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1344:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1346:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1348:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x134A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x134C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x134E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1350:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1352:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1354:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1356:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1358:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x135A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x135C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x135E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1360:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1362:		in r11,  0x0	 ;In Port Rd<-P
0x1364:		in r27,  0x1	 ;In Port Rd<-P
0x1366:		in r11,  0x12	 ;In Port Rd<-P
0x1368:		in r27,  0x13	 ;In Port Rd<-P
0x136A:		in r11,  0x24	 ;In Port Rd<-P
0x136C:		in r27,  0x25	 ;In Port Rd<-P
0x136E:		in r11,  0x36	 ;In Port Rd<-P
0x1370:		in r27,  0x37	 ;In Port Rd<-P
0x1372:		out  0x8, r11	 ;Out Port    P<-Rr
0x1374:		out  0x9, r27	 ;Out Port    P<-Rr
0x1376:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1378:		out  0x1B, r27	 ;Out Port    P<-Rr
0x137A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x137C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x137E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1380:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1382:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1504  
0x1384:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1708  
0x1386:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x190C  
0x1388:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1B10  
0x138A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1D14  
0x138C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x1F18  
0x138E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x211C  
0x1390:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2320  
0x1392:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0x524  
0x1394:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x728  
0x1396:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x92C  
0x1398:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xB30  
0x139A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0xD34  
0x139C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0xF38  
0x139E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x113C  
0x13A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1340  
0x13A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1544  
0x13A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1748  
0x13A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x194C  
0x13A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1B50  
0x13AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1D54  
0x13AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x1F58  
0x13AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x215C  
0x13B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2360  
0x13B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0x564  
0x13B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x768  
0x13B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x96C  
0x13B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xB70  
0x13BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0xD74  
0x13BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0xF78  
0x13BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x117C  
0x13C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1380  
0x13C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x13C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x13C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x13C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x13CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x13CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x13CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x13D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x13D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x13D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x13D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x13D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x13DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x13DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x13DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x13E0:		ser r30		 ;Set Register    Rd<-$FF
0x13E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1420
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x13E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1462
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x13E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x13A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x13E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x13E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x13EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1428
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x13EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x146A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x13EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x13AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x13F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x13EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x13F2:		;Unknown command CODE: 0xF8F8
0x13F4:		;Unknown command CODE: 0xF9F9
0x13F6:		;Unknown command CODE: 0xFAFA
0x13F8:		;Unknown command CODE: 0xFBFB
0x13FA:		;Unknown command CODE: 0xFCFC
0x13FC:		;Unknown command CODE: 0xFDFD
0x13FE:		;Unknown command CODE: 0xFEFE
0x1400:		;Unknown command CODE: 0xFFFF
0x1402:		nop		;No operation
0x1404:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1406:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1408:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x140A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x140C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x140E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1410:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1412:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1414:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1416:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1418:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x141A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x141C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x141E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1420:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1422:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1424:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1426:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1428:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x142A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x142C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x142E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1430:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1432:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1434:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1436:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1438:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x143A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x143C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x143E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1440:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1442:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1444:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1446:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1448:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x144A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x144C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x144E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1450:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1452:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1454:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1456:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1458:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x145A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x145C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x145E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1460:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1462:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1464:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1466:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1468:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x146A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x146C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x146E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1470:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1472:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1474:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1476:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1478:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x147A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x147C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x147E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1480:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1482:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1484:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1486:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1488:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x148A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x148C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x148E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1490:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1492:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1494:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1496:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1498:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x149A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x149C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x149E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x14A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x14A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x14A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x14A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x14A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x14AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x14AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x14AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x14B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x14B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x14B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x14B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x14B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x14BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x14BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x14BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x14C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x14C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x14E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x14FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1500:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1502:		ld r8, Z	 ;Load Indirect  
0x1504:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1506:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1508:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x150A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x150C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x150E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1510:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1512:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1514:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1516:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1518:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x151A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x151C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x151E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1520:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1522:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1526:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1528:		;Unknown command CODE: 0x9393
0x152A:		;Unknown command CODE: 0x9494
0x152C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x152E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1530:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1532:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1534:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1536:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1538:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x153A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x153C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x153E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1540:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1542:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1544:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1546:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1548:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x154A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x154C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x154E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1550:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1552:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1554:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1556:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1558:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x155A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x155C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x155E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1560:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1562:		in r11,  0x0	 ;In Port Rd<-P
0x1564:		in r27,  0x1	 ;In Port Rd<-P
0x1566:		in r11,  0x12	 ;In Port Rd<-P
0x1568:		in r27,  0x13	 ;In Port Rd<-P
0x156A:		in r11,  0x24	 ;In Port Rd<-P
0x156C:		in r27,  0x25	 ;In Port Rd<-P
0x156E:		in r11,  0x36	 ;In Port Rd<-P
0x1570:		in r27,  0x37	 ;In Port Rd<-P
0x1572:		out  0x8, r11	 ;Out Port    P<-Rr
0x1574:		out  0x9, r27	 ;Out Port    P<-Rr
0x1576:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1578:		out  0x1B, r27	 ;Out Port    P<-Rr
0x157A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x157C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x157E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1580:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1582:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1704  
0x1584:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1908  
0x1586:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x1B0C  
0x1588:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1D10  
0x158A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x1F14  
0x158C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x2118  
0x158E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x231C  
0x1590:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2520  
0x1592:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0x724  
0x1594:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x928  
0x1596:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xB2C  
0x1598:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xD30  
0x159A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0xF34  
0x159C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x1138  
0x159E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x133C  
0x15A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1540  
0x15A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1744  
0x15A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1948  
0x15A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x1B4C  
0x15A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1D50  
0x15AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x1F54  
0x15AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x2158  
0x15AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x235C  
0x15B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2560  
0x15B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0x764  
0x15B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x968  
0x15B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xB6C  
0x15B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xD70  
0x15BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0xF74  
0x15BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x1178  
0x15BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x137C  
0x15C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1580  
0x15C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x15C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x15C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x15C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x15CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x15CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x15CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x15D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x15D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x15D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x15D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x15D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x15DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x15DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x15DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x15E0:		ser r30		 ;Set Register    Rd<-$FF
0x15E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1620
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x15E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1662
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x15E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x15A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x15E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x15E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x15EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1628
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x15EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x166A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x15EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x15AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x15F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x15EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x15F2:		;Unknown command CODE: 0xF8F8
0x15F4:		;Unknown command CODE: 0xF9F9
0x15F6:		;Unknown command CODE: 0xFAFA
0x15F8:		;Unknown command CODE: 0xFBFB
0x15FA:		;Unknown command CODE: 0xFCFC
0x15FC:		;Unknown command CODE: 0xFDFD
0x15FE:		;Unknown command CODE: 0xFEFE
0x1600:		;Unknown command CODE: 0xFFFF
0x1602:		nop		;No operation
0x1604:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1606:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1608:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x160A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x160C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x160E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1610:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1612:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1614:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1616:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1618:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x161A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x161C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x161E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1620:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1622:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1624:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1626:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1628:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x162A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x162C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x162E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1630:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1632:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1634:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1636:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1638:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x163A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x163C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x163E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1640:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1642:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1644:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1646:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1648:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x164A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x164C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x164E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1650:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1652:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1654:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1656:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1658:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x165A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x165C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x165E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1660:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1662:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1664:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1666:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1668:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x166A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x166C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x166E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1670:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1672:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1674:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1676:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1678:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x167A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x167C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x167E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1680:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1682:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1684:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1686:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1688:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x168A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x168C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x168E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1690:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1692:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1694:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1696:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1698:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x169A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x169C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x169E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x16A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x16A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x16A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x16A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x16A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x16AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x16AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x16AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x16B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x16B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x16B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x16B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x16B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x16BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x16BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x16BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x16C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x16C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x16E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x16FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1700:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1702:		ld r8, Z	 ;Load Indirect  
0x1704:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1706:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1708:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x170A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x170C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x170E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1710:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1712:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1714:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1716:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1718:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x171A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x171C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x171E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1720:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1722:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1726:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1728:		;Unknown command CODE: 0x9393
0x172A:		;Unknown command CODE: 0x9494
0x172C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x172E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1730:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1732:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1734:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1736:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1738:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x173A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x173C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x173E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1740:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1742:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1744:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1746:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1748:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x174A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x174C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x174E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1750:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1752:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1754:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1756:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1758:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x175A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x175C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x175E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1760:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1762:		in r11,  0x0	 ;In Port Rd<-P
0x1764:		in r27,  0x1	 ;In Port Rd<-P
0x1766:		in r11,  0x12	 ;In Port Rd<-P
0x1768:		in r27,  0x13	 ;In Port Rd<-P
0x176A:		in r11,  0x24	 ;In Port Rd<-P
0x176C:		in r27,  0x25	 ;In Port Rd<-P
0x176E:		in r11,  0x36	 ;In Port Rd<-P
0x1770:		in r27,  0x37	 ;In Port Rd<-P
0x1772:		out  0x8, r11	 ;Out Port    P<-Rr
0x1774:		out  0x9, r27	 ;Out Port    P<-Rr
0x1776:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1778:		out  0x1B, r27	 ;Out Port    P<-Rr
0x177A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x177C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x177E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1780:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1782:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1904  
0x1784:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1B08  
0x1786:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x1D0C  
0x1788:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x1F10  
0x178A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x2114  
0x178C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x2318  
0x178E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x251C  
0x1790:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2720  
0x1792:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0x924  
0x1794:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xB28  
0x1796:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xD2C  
0x1798:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0xF30  
0x179A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x1134  
0x179C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x1338  
0x179E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x153C  
0x17A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1740  
0x17A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1944  
0x17A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1B48  
0x17A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x1D4C  
0x17A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x1F50  
0x17AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x2154  
0x17AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x2358  
0x17AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x255C  
0x17B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2760  
0x17B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0x964  
0x17B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xB68  
0x17B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xD6C  
0x17B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0xF70  
0x17BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x1174  
0x17BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x1378  
0x17BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x157C  
0x17C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1780  
0x17C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x17C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x17C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x17C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x17CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x17CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x17CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x17D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x17D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x17D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x17D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x17D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x17DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x17DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x17DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x17E0:		ser r30		 ;Set Register    Rd<-$FF
0x17E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1820
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x17E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1862
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x17E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x17A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x17E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x17E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x17EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1828
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x17EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x186A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x17EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x17AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x17F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x17EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x17F2:		;Unknown command CODE: 0xF8F8
0x17F4:		;Unknown command CODE: 0xF9F9
0x17F6:		;Unknown command CODE: 0xFAFA
0x17F8:		;Unknown command CODE: 0xFBFB
0x17FA:		;Unknown command CODE: 0xFCFC
0x17FC:		;Unknown command CODE: 0xFDFD
0x17FE:		;Unknown command CODE: 0xFEFE
0x1800:		;Unknown command CODE: 0xFFFF
0x1802:		nop		;No operation
0x1804:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1806:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1808:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x180A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x180C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x180E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1810:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1812:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1814:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1816:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1818:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x181A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x181C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x181E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1820:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1822:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1824:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1826:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1828:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x182A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x182C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x182E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1830:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1832:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1834:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1836:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1838:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x183A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x183C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x183E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1840:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1842:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1844:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1846:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1848:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x184A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x184C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x184E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1850:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1852:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1854:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1856:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1858:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x185A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x185C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x185E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1860:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1862:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1864:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1866:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1868:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x186A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x186C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x186E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1870:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1872:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1874:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1876:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1878:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x187A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x187C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x187E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1880:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1882:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1884:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1886:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1888:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x188A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x188C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x188E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1890:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1892:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1894:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1896:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1898:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x189A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x189C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x189E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x18A0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x18A2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x18A4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x18A6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x18A8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x18AA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x18AC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x18AE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x18B0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x18B2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x18B4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x18B6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x18B8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x18BA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x18BC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x18BE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x18C0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x18C2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18C4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18C6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18C8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18CA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18CC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18CE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18D0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18D2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18D4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18D6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18D8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18DA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18DC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18DE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18E0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x18E2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18E4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18E6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18E8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18EA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18EC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18EE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18F0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18F2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18F4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18F6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18F8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18FA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18FC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x18FE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1900:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1902:		ld r8, Z	 ;Load Indirect  
0x1904:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1906:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1908:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x190A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x190C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x190E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1910:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1912:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1914:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1916:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1918:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x191A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x191C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x191E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1920:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1922:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1926:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1928:		;Unknown command CODE: 0x9393
0x192A:		;Unknown command CODE: 0x9494
0x192C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x192E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1930:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1932:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1934:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1936:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1938:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x193A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x193C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x193E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1940:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1942:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1944:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1946:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1948:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x194A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x194C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x194E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1950:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1952:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1954:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1956:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1958:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x195A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x195C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x195E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1960:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1962:		in r11,  0x0	 ;In Port Rd<-P
0x1964:		in r27,  0x1	 ;In Port Rd<-P
0x1966:		in r11,  0x12	 ;In Port Rd<-P
0x1968:		in r27,  0x13	 ;In Port Rd<-P
0x196A:		in r11,  0x24	 ;In Port Rd<-P
0x196C:		in r27,  0x25	 ;In Port Rd<-P
0x196E:		in r11,  0x36	 ;In Port Rd<-P
0x1970:		in r27,  0x37	 ;In Port Rd<-P
0x1972:		out  0x8, r11	 ;Out Port    P<-Rr
0x1974:		out  0x9, r27	 ;Out Port    P<-Rr
0x1976:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1978:		out  0x1B, r27	 ;Out Port    P<-Rr
0x197A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x197C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x197E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1980:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1982:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1B04  
0x1984:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1D08  
0x1986:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x1F0C  
0x1988:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x2110  
0x198A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x2314  
0x198C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x2518  
0x198E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x271C  
0x1990:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2920  
0x1992:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xB24  
0x1994:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xD28  
0x1996:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0xF2C  
0x1998:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x1130  
0x199A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x1334  
0x199C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x1538  
0x199E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x173C  
0x19A0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1940  
0x19A2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1B44  
0x19A4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1D48  
0x19A6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x1F4C  
0x19A8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x2150  
0x19AA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x2354  
0x19AC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x2558  
0x19AE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x275C  
0x19B0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2960  
0x19B2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xB64  
0x19B4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xD68  
0x19B6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0xF6C  
0x19B8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x1170  
0x19BA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x1374  
0x19BC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x1578  
0x19BE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x177C  
0x19C0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1980  
0x19C2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x19C4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x19C6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x19C8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x19CA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x19CC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x19CE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x19D0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x19D2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x19D4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x19D6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x19D8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x19DA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x19DC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x19DE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x19E0:		ser r30		 ;Set Register    Rd<-$FF
0x19E2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1A20
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x19E4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1A62
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x19E6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x19A4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x19E8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x19E6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x19EA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1A28
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x19EC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x1A6A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x19EE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x19AC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x19F0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x19EE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x19F2:		;Unknown command CODE: 0xF8F8
0x19F4:		;Unknown command CODE: 0xF9F9
0x19F6:		;Unknown command CODE: 0xFAFA
0x19F8:		;Unknown command CODE: 0xFBFB
0x19FA:		;Unknown command CODE: 0xFCFC
0x19FC:		;Unknown command CODE: 0xFDFD
0x19FE:		;Unknown command CODE: 0xFEFE
0x1A00:		;Unknown command CODE: 0xFFFF
0x1A02:		nop		;No operation
0x1A04:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1A06:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1A08:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x1A0A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x1A0C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x1A0E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1A10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1A12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1A14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1A16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1A18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1A1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x1A1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x1A1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1A20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1A22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1A24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1A26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1A28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1A2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1A34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1A36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1A38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x1A3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1A42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1A44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1A46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1A48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x1A4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x1A4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x1A4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1A50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1A52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1A54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1A56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1A58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x1A5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x1A5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x1A5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1A60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1A62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1A64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1A66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1A68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x1A6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x1A6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x1A6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1A70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1A72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1A74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1A76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1A78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x1A7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x1A7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x1A7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1A80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1A82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1A9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1AA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1AA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x1AA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x1AA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x1AA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x1AAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x1AAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x1AAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x1AB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x1AB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x1AB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x1AB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x1AB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x1ABA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x1ABC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x1ABE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x1AC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x1AC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ACA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ACC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ACE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AD0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AD2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AD4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AD6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AD8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ADA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ADC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ADE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1AE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1AFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1B00:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1B02:		ld r8, Z	 ;Load Indirect  
0x1B04:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1B06:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1B08:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x1B0A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x1B0C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x1B0E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1B10:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1B12:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1B14:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1B16:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1B18:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x1B1A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x1B1C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x1B1E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1B20:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1B22:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1B26:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1B28:		;Unknown command CODE: 0x9393
0x1B2A:		;Unknown command CODE: 0x9494
0x1B2C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x1B2E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1B30:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1B32:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1B34:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1B36:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1B38:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x1B3A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1B3C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1B3E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1B40:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1B42:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1B44:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1B46:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1B48:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x1B4A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x1B4C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x1B4E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1B50:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1B52:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1B54:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1B56:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1B58:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x1B5A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x1B5C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x1B5E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1B60:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1B62:		in r11,  0x0	 ;In Port Rd<-P
0x1B64:		in r27,  0x1	 ;In Port Rd<-P
0x1B66:		in r11,  0x12	 ;In Port Rd<-P
0x1B68:		in r27,  0x13	 ;In Port Rd<-P
0x1B6A:		in r11,  0x24	 ;In Port Rd<-P
0x1B6C:		in r27,  0x25	 ;In Port Rd<-P
0x1B6E:		in r11,  0x36	 ;In Port Rd<-P
0x1B70:		in r27,  0x37	 ;In Port Rd<-P
0x1B72:		out  0x8, r11	 ;Out Port    P<-Rr
0x1B74:		out  0x9, r27	 ;Out Port    P<-Rr
0x1B76:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1B78:		out  0x1B, r27	 ;Out Port    P<-Rr
0x1B7A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x1B7C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x1B7E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1B80:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1B82:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1D04  
0x1B84:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x1F08  
0x1B86:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x210C  
0x1B88:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x2310  
0x1B8A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x2514  
0x1B8C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x2718  
0x1B8E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x291C  
0x1B90:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2B20  
0x1B92:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xD24  
0x1B94:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0xF28  
0x1B96:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x112C  
0x1B98:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x1330  
0x1B9A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x1534  
0x1B9C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x1738  
0x1B9E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x193C  
0x1BA0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1B40  
0x1BA2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1D44  
0x1BA4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x1F48  
0x1BA6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x214C  
0x1BA8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x2350  
0x1BAA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x2554  
0x1BAC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x2758  
0x1BAE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x295C  
0x1BB0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2B60  
0x1BB2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xD64  
0x1BB4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0xF68  
0x1BB6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x116C  
0x1BB8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x1370  
0x1BBA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x1574  
0x1BBC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x1778  
0x1BBE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x197C  
0x1BC0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1B80  
0x1BC2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x1BC4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x1BC6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x1BC8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x1BCA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x1BCC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x1BCE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x1BD0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x1BD2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x1BD4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x1BD6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x1BD8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x1BDA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x1BDC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x1BDE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x1BE0:		ser r30		 ;Set Register    Rd<-$FF
0x1BE2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1C20
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x1BE4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1C62
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x1BE6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x1BA4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x1BE8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x1BE6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x1BEA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1C28
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x1BEC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x1C6A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x1BEE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x1BAC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x1BF0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x1BEE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x1BF2:		;Unknown command CODE: 0xF8F8
0x1BF4:		;Unknown command CODE: 0xF9F9
0x1BF6:		;Unknown command CODE: 0xFAFA
0x1BF8:		;Unknown command CODE: 0xFBFB
0x1BFA:		;Unknown command CODE: 0xFCFC
0x1BFC:		;Unknown command CODE: 0xFDFD
0x1BFE:		;Unknown command CODE: 0xFEFE
0x1C00:		;Unknown command CODE: 0xFFFF
0x1C02:		nop		;No operation
0x1C04:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1C06:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1C08:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x1C0A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x1C0C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x1C0E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1C10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1C12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1C14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1C16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1C18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1C1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x1C1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x1C1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1C20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1C22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1C24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1C26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1C28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1C2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1C34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1C36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1C38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x1C3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1C42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1C44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1C46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1C48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x1C4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x1C4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x1C4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1C50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1C52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1C54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1C56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1C58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x1C5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x1C5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x1C5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1C60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1C62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1C64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1C66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1C68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x1C6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x1C6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x1C6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1C70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1C72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1C74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1C76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1C78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x1C7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x1C7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x1C7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1C80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1C82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1C9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1CA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1CA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x1CA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x1CA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x1CA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x1CAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x1CAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x1CAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x1CB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x1CB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x1CB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x1CB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x1CB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x1CBA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x1CBC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x1CBE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x1CC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x1CC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CCA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CCC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CCE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CD0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CD2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CD4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CD6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CD8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CDA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CDC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CDE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1CE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1CFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1D00:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1D02:		ld r8, Z	 ;Load Indirect  
0x1D04:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1D06:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1D08:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x1D0A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x1D0C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x1D0E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1D10:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1D12:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1D14:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1D16:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1D18:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x1D1A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x1D1C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x1D1E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1D20:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1D22:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1D26:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1D28:		;Unknown command CODE: 0x9393
0x1D2A:		;Unknown command CODE: 0x9494
0x1D2C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x1D2E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1D30:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1D32:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1D34:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1D36:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1D38:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x1D3A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1D3C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1D3E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1D40:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1D42:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1D44:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1D46:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1D48:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x1D4A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x1D4C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x1D4E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1D50:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1D52:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1D54:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1D56:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1D58:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x1D5A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x1D5C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x1D5E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1D60:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1D62:		in r11,  0x0	 ;In Port Rd<-P
0x1D64:		in r27,  0x1	 ;In Port Rd<-P
0x1D66:		in r11,  0x12	 ;In Port Rd<-P
0x1D68:		in r27,  0x13	 ;In Port Rd<-P
0x1D6A:		in r11,  0x24	 ;In Port Rd<-P
0x1D6C:		in r27,  0x25	 ;In Port Rd<-P
0x1D6E:		in r11,  0x36	 ;In Port Rd<-P
0x1D70:		in r27,  0x37	 ;In Port Rd<-P
0x1D72:		out  0x8, r11	 ;Out Port    P<-Rr
0x1D74:		out  0x9, r27	 ;Out Port    P<-Rr
0x1D76:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1D78:		out  0x1B, r27	 ;Out Port    P<-Rr
0x1D7A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x1D7C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x1D7E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1D80:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1D82:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x1F04  
0x1D84:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x2108  
0x1D86:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x230C  
0x1D88:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x2510  
0x1D8A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x2714  
0x1D8C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x2918  
0x1D8E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x2B1C  
0x1D90:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2D20  
0x1D92:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0xF24  
0x1D94:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x1128  
0x1D96:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x132C  
0x1D98:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x1530  
0x1D9A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x1734  
0x1D9C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x1938  
0x1D9E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x1B3C  
0x1DA0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1D40  
0x1DA2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x1F44  
0x1DA4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x2148  
0x1DA6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x234C  
0x1DA8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x2550  
0x1DAA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x2754  
0x1DAC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x2958  
0x1DAE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x2B5C  
0x1DB0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2D60  
0x1DB2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0xF64  
0x1DB4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x1168  
0x1DB6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x136C  
0x1DB8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x1570  
0x1DBA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x1774  
0x1DBC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x1978  
0x1DBE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x1B7C  
0x1DC0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1D80  
0x1DC2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x1DC4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x1DC6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x1DC8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x1DCA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x1DCC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x1DCE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x1DD0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x1DD2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x1DD4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x1DD6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x1DD8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x1DDA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x1DDC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x1DDE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x1DE0:		ser r30		 ;Set Register    Rd<-$FF
0x1DE2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x1E20
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x1DE4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x1E62
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x1DE6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x1DA4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x1DE8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x1DE6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x1DEA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x1E28
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x1DEC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x1E6A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x1DEE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x1DAC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x1DF0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x1DEE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x1DF2:		;Unknown command CODE: 0xF8F8
0x1DF4:		;Unknown command CODE: 0xF9F9
0x1DF6:		;Unknown command CODE: 0xFAFA
0x1DF8:		;Unknown command CODE: 0xFBFB
0x1DFA:		;Unknown command CODE: 0xFCFC
0x1DFC:		;Unknown command CODE: 0xFDFD
0x1DFE:		;Unknown command CODE: 0xFEFE
0x1E00:		;Unknown command CODE: 0xFFFF
0x1E02:		nop		;No operation
0x1E04:		movw r0, r2	 ;Copy Register Word  Rd+1:Rd<-Rr+1:Rr
0x1E06:		muls r16, r18	 ;Multiply Signed R1:R0<-RdxRr
0x1E08:		mulsu r16, r19	 ;Multiply Signed with Unsigned   R1:R0<-RdxRr
0x1E0A:		cpc r0, r4	 ;Compare with Carry  Rd-Rr-C
0x1E0C:		cpc r16, r5	 ;Compare with Carry  Rd-Rr-C
0x1E0E:		cpc r0, r22	 ;Compare with Carry  Rd-Rr-C
0x1E10:		cpc r16, r23	 ;Compare with Carry  Rd-Rr-C
0x1E12:		sbc r0, r8	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1E14:		sbc r16, r9	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1E16:		sbc r0, r26	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1E18:		sbc r16, r27	 ;Subtract with Carry two Registers   Rd<-Rd-Rr-C
0x1E1A:		add r0, r12	 ;Add two Registers   Rd <- Rd + Rr
0x1E1C:		add r16, r13	 ;Add two Registers   Rd <- Rd + Rr
0x1E1E:		add r0, r30	 ;Add two Registers   Rd <- Rd + Rr
0x1E20:		add r16, r31	 ;Add two Registers   Rd <- Rd + Rr
0x1E22:		cpse r1, r0	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1E24:		cpse r17, r1	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1E26:		cpse r1, r18	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1E28:		cpse r17, r19	 ;Compare, Skip if Equal  if(Rd=Rr)PC<-PC + 2or3
0x1E2A:		cp r1, r4	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E2C:		cp r17, r5	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E2E:		cp r1, r22	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E30:		cp r17, r23	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E32:		sub r1, r8	 ;Subtract two Registers  Rd <- Rd - Rr
0x1E34:		sub r17, r9	 ;Subtract two Registers  Rd <- Rd - Rr
0x1E36:		sub r1, r26	 ;Subtract two Registers  Rd <- Rd - Rr
0x1E38:		sub r17, r27	 ;Subtract two Registers  Rd <- Rd - Rr
0x1E3A:		adc r1, r12	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r12	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E3C:		adc r17, r13	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r13	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E3E:		adc r1, r30	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r1, r30	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E40:		adc r17, r31	 ;Add with Carry two Registers    Rd <- Rd + Rr + C
		;Variant 2 =>> rol r17, r31	 ;Rotate Left Through Carry   Rd(0)<-C,Rd(n+1)<- Rd(n),C<-Rd(7)
0x1E42:		tst r2, r0	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r0	 ;Logical AND Registers   Rd <- Rd . Rr
0x1E44:		tst r18, r1	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r1	 ;Logical AND Registers   Rd <- Rd . Rr
0x1E46:		tst r2, r18	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r2, r18	 ;Logical AND Registers   Rd <- Rd . Rr
0x1E48:		tst r18, r19	 ;Test for Zero or Minus  Rd <- Rd . Rd
		; equivalent function = and r18, r19	 ;Logical AND Registers   Rd <- Rd . Rr
0x1E4A:		eor r2, r4	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r36	 ;Clear Register  Rd <- Rd ffi Rd
0x1E4C:		eor r18, r5	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r293	 ;Clear Register  Rd <- Rd ffi Rd
0x1E4E:		eor r2, r22	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r550	 ;Clear Register  Rd <- Rd ffi Rd
0x1E50:		eor r18, r23	 ;Exclusive OR Registers  Rd <- Rd ffl Rr
		; equivalent function = clr r807	 ;Clear Register  Rd <- Rd ffi Rd
0x1E52:		or r2, r8	 ;Logical OR Registers    Rd <- Rd v Rr
0x1E54:		or r18, r9	 ;Logical OR Registers    Rd <- Rd v Rr
0x1E56:		or r2, r26	 ;Logical OR Registers    Rd <- Rd v Rr
0x1E58:		or r18, r27	 ;Logical OR Registers    Rd <- Rd v Rr
0x1E5A:		mov r2, r12	 ;Move Between Registers  Rd<-Rr
0x1E5C:		mov r18, r13	 ;Move Between Registers  Rd<-Rr
0x1E5E:		mov r2, r30	 ;Move Between Registers  Rd<-Rr
0x1E60:		mov r18, r31	 ;Move Between Registers  Rd<-Rr
0x1E62:		cpi r19,  0x10	 ;Compare Register with Immediate Rd-K
0x1E64:		cpi r19,  0x91	 ;Compare Register with Immediate Rd-K
0x1E66:		cpi r19,  0x12	 ;Compare Register with Immediate Rd-K
0x1E68:		cpi r19,  0x93	 ;Compare Register with Immediate Rd-K
0x1E6A:		cpi r19,  0x14	 ;Compare Register with Immediate Rd-K
0x1E6C:		cpi r19,  0x95	 ;Compare Register with Immediate Rd-K
0x1E6E:		cpi r19,  0x16	 ;Compare Register with Immediate Rd-K
0x1E70:		cpi r19,  0x97	 ;Compare Register with Immediate Rd-K
0x1E72:		cpi r19,  0x18	 ;Compare Register with Immediate Rd-K
0x1E74:		cpi r19,  0x99	 ;Compare Register with Immediate Rd-K
0x1E76:		cpi r19,  0x1A	 ;Compare Register with Immediate Rd-K
0x1E78:		cpi r19,  0x9B	 ;Compare Register with Immediate Rd-K
0x1E7A:		cpi r19,  0x1C	 ;Compare Register with Immediate Rd-K
0x1E7C:		cpi r19,  0x9D	 ;Compare Register with Immediate Rd-K
0x1E7E:		cpi r19,  0x1E	 ;Compare Register with Immediate Rd-K
0x1E80:		cpi r19,  0x9F	 ;Compare Register with Immediate Rd-K
0x1E82:		sbci r20,  0x20	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E84:		sbci r20,  0xA1	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E86:		sbci r20,  0x22	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E88:		sbci r20,  0xA3	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E8A:		sbci r20,  0x24	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E8C:		sbci r20,  0xA5	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E8E:		sbci r20,  0x26	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E90:		sbci r20,  0xA7	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E92:		sbci r20,  0x28	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E94:		sbci r20,  0xA9	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E96:		sbci r20,  0x2A	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E98:		sbci r20,  0xAB	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E9A:		sbci r20,  0x2C	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E9C:		sbci r20,  0xAD	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1E9E:		sbci r20,  0x2E	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1EA0:		sbci r20,  0xAF	 ;Subtract with Carry Constant from Reg.  Rd <- Rd - K - C
0x1EA2:		subi r21,  0x20	 ;Subtract Constant from Register Rd <- Rd - K
0x1EA4:		subi r21,  0xA1	 ;Subtract Constant from Register Rd <- Rd - K
0x1EA6:		subi r21,  0x22	 ;Subtract Constant from Register Rd <- Rd - K
0x1EA8:		subi r21,  0xA3	 ;Subtract Constant from Register Rd <- Rd - K
0x1EAA:		subi r21,  0x24	 ;Subtract Constant from Register Rd <- Rd - K
0x1EAC:		subi r21,  0xA5	 ;Subtract Constant from Register Rd <- Rd - K
0x1EAE:		subi r21,  0x26	 ;Subtract Constant from Register Rd <- Rd - K
0x1EB0:		subi r21,  0xA7	 ;Subtract Constant from Register Rd <- Rd - K
0x1EB2:		subi r21,  0x28	 ;Subtract Constant from Register Rd <- Rd - K
0x1EB4:		subi r21,  0xA9	 ;Subtract Constant from Register Rd <- Rd - K
0x1EB6:		subi r21,  0x2A	 ;Subtract Constant from Register Rd <- Rd - K
0x1EB8:		subi r21,  0xAB	 ;Subtract Constant from Register Rd <- Rd - K
0x1EBA:		subi r21,  0x2C	 ;Subtract Constant from Register Rd <- Rd - K
0x1EBC:		subi r21,  0xAD	 ;Subtract Constant from Register Rd <- Rd - K
0x1EBE:		subi r21,  0x2E	 ;Subtract Constant from Register Rd <- Rd - K
0x1EC0:		subi r21,  0xAF	 ;Subtract Constant from Register Rd <- Rd - K
0x1EC2:		ori r22,  0x30	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x30	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EC4:		ori r22,  0xB1	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB1	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EC6:		ori r22,  0x32	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x32	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EC8:		ori r22,  0xB3	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB3	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ECA:		ori r22,  0x34	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x34	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ECC:		ori r22,  0xB5	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB5	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ECE:		ori r22,  0x36	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x36	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ED0:		ori r22,  0xB7	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB7	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ED2:		ori r22,  0x38	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x38	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ED4:		ori r22,  0xB9	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xB9	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ED6:		ori r22,  0x3A	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3A	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1ED8:		ori r22,  0xBB	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBB	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EDA:		ori r22,  0x3C	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3C	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EDC:		ori r22,  0xBD	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBD	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EDE:		ori r22,  0x3E	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0x3E	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EE0:		ori r22,  0xBF	 ;Logical OR Register and Constant    Rd <- Rd v K
		; equivalent function = sbr r22,  0xBF	 ;Set Bit(s) in Register  Rd <- Rd v K
		; more: http://ddn.at.ua/
0x1EE2:		andi r23,  0x0	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x0	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EE4:		andi r23,  0x11	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x11	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EE6:		andi r23,  0x22	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x22	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EE8:		andi r23,  0x33	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x33	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EEA:		andi r23,  0x44	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x44	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EEC:		andi r23,  0x55	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x55	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EEE:		andi r23,  0x66	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x66	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EF0:		andi r23,  0x77	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x77	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EF2:		andi r23,  0x88	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x88	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EF4:		andi r23,  0x99	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0x99	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EF6:		andi r23,  0xAA	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xAA	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EF8:		andi r23,  0xBB	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xBB	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EFA:		andi r23,  0xCC	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xCC	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EFC:		andi r23,  0xDD	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xDD	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1EFE:		andi r23,  0xEE	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xEE	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1F00:		andi r23,  0xFF	 ;Logical AND Register and Constant   Rd <- Rd & K
		; equivalent function = cbr r23,  0xFF	 ;Clear Bit(s) in Register    Rd <- Rd & ($FF - K)
		; more: http://ddn.at.ua/
0x1F02:		ld r8, Z	 ;Load Indirect  
0x1F04:		ldd r8, Z+ 0x1	 ;Load Indirect with Displacement
0x1F06:		std Z+ 0x2, r8		 ;Store Indirect with Displacement
0x1F08:		std Z+ 0x3, r8		 ;Store Indirect with Displacement
0x1F0A:		ldd r8, Z+ 0xC	 ;Load Indirect with Displacement
0x1F0C:		ldd r8, Z+ 0xD	 ;Load Indirect with Displacement
0x1F0E:		std Z+ 0xE, r8		 ;Store Indirect with Displacement
0x1F10:		std Z+ 0xF, r8		 ;Store Indirect with Displacement
0x1F12:		ldd r8, Y+ 0x10	 ;Load Indirect with Displacement
0x1F14:		ldd r8, Y+ 0x11	 ;Load Indirect with Displacement
0x1F16:		std Y+ 0x12, r8		 ;Store Indirect with Displacement
0x1F18:		std Y+ 0x13, r8		 ;Store Indirect with Displacement
0x1F1A:		ldd r8, Y+ 0x1C	 ;Load Indirect with Displacement
0x1F1C:		ldd r8, Y+ 0x1D	 ;Load Indirect with Displacement
0x1F1E:		std Y+ 0x1E, r8		 ;Store Indirect with Displacement
0x1F20:		std Y+ 0x1F, r8		 ;Store Indirect with Displacement
0x1F22:		lds r9,  0x9191	 ;Load Direct from SRAM   Rd <-(k)
0x1F26:		st -Z, r9		 ;Load Indirect  ;Store Indirect
0x1F28:		;Unknown command CODE: 0x9393
0x1F2A:		;Unknown command CODE: 0x9494
0x1F2C:		asr r25		 ;Arithmetic Shift Right  Rd(n)<-Rd(n+1), n=0:6
0x1F2E:		adiw r26,  0x26	 ;Add Immediate to Word   Rdh:Rdl<-Rdh:Rdl+K
0x1F30:		sbiw r26,  0x27	 ;Subtract Immediate from Word    Rdh:Rdl <- Rdh:Rdl - K
0x1F32:		cbi  0x13,  0x0	 ;Clear Bit in I/O Register   l/O(P,b)<-0
0x1F34:		sbic  0x1, r 0x6	 ;Skip if Bit in I/O Register Cleared if (P(b)=0) PC<-PC + 2or3
0x1F36:		sbi  0x13,  0x2	 ;Set Bit in I/O Register l/O(P,b) <-1
0x1F38:		sbis  0x3, r 0xE	 ;Skip if Bit in I/O Register is Set  if (P(b)=1 )PC<-PC + 2or3
0x1F3A:		mul r9, r12	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1F3C:		mul r25, r13	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1F3E:		mul r9, r30	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1F40:		mul r25, r31	 ;Multiply Unsigned   R1:R0<-RdxRr
0x1F42:		ldd r10, Z+ 0x20	 ;Load Indirect with Displacement
0x1F44:		ldd r10, Z+ 0x21	 ;Load Indirect with Displacement
0x1F46:		std Z+ 0x22, r10		 ;Store Indirect with Displacement
0x1F48:		std Z+ 0x23, r10		 ;Store Indirect with Displacement
0x1F4A:		ldd r10, Z+ 0x2C	 ;Load Indirect with Displacement
0x1F4C:		ldd r10, Z+ 0x2D	 ;Load Indirect with Displacement
0x1F4E:		std Z+ 0x2E, r10		 ;Store Indirect with Displacement
0x1F50:		std Z+ 0x2F, r10		 ;Store Indirect with Displacement
0x1F52:		ldd r10, Y+ 0x30	 ;Load Indirect with Displacement
0x1F54:		ldd r10, Y+ 0x31	 ;Load Indirect with Displacement
0x1F56:		std Y+ 0x32, r10		 ;Store Indirect with Displacement
0x1F58:		std Y+ 0x33, r10		 ;Store Indirect with Displacement
0x1F5A:		ldd r10, Y+ 0x3C	 ;Load Indirect with Displacement
0x1F5C:		ldd r10, Y+ 0x3D	 ;Load Indirect with Displacement
0x1F5E:		std Y+ 0x3E, r10		 ;Store Indirect with Displacement
0x1F60:		std Y+ 0x3F, r10		 ;Store Indirect with Displacement
0x1F62:		in r11,  0x0	 ;In Port Rd<-P
0x1F64:		in r27,  0x1	 ;In Port Rd<-P
0x1F66:		in r11,  0x12	 ;In Port Rd<-P
0x1F68:		in r27,  0x13	 ;In Port Rd<-P
0x1F6A:		in r11,  0x24	 ;In Port Rd<-P
0x1F6C:		in r27,  0x25	 ;In Port Rd<-P
0x1F6E:		in r11,  0x36	 ;In Port Rd<-P
0x1F70:		in r27,  0x37	 ;In Port Rd<-P
0x1F72:		out  0x8, r11	 ;Out Port    P<-Rr
0x1F74:		out  0x9, r27	 ;Out Port    P<-Rr
0x1F76:		out  0x1A, r11	 ;Out Port    P<-Rr
0x1F78:		out  0x1B, r27	 ;Out Port    P<-Rr
0x1F7A:		out  0x2C, r11	 ;Out Port    P<-Rr
0x1F7C:		out  0x2D, r27	 ;Out Port    P<-Rr
0x1F7E:		out  0x3E, r11	 ;Out Port    P<-Rr
0x1F80:		out  0x3F, r27	 ;Out Port    P<-Rr
0x1F82:		rjmp +0x180	 ;Relative Jump   PC<-PC + k +1, send to 0x2104  
0x1F84:		rjmp +0x382	 ;Relative Jump   PC<-PC + k +1, send to 0x2308  
0x1F86:		rjmp +0x584	 ;Relative Jump   PC<-PC + k +1, send to 0x250C  
0x1F88:		rjmp +0x786	 ;Relative Jump   PC<-PC + k +1, send to 0x2710  
0x1F8A:		rjmp +0x988	 ;Relative Jump   PC<-PC + k +1, send to 0x2914  
0x1F8C:		rjmp +0xB8A	 ;Relative Jump   PC<-PC + k +1, send to 0x2B18  
0x1F8E:		rjmp +0xD8C	 ;Relative Jump   PC<-PC + k +1, send to 0x2D1C  
0x1F90:		rjmp +0xF8E	 ;Relative Jump   PC<-PC + k +1, send to 0x2F20  
0x1F92:		rjmp -0xE70	 ;Relative Jump   PC<-PC + k +1, send to 0x1124  
0x1F94:		rjmp -0xC6E	 ;Relative Jump   PC<-PC + k +1, send to 0x1328  
0x1F96:		rjmp -0xA6C	 ;Relative Jump   PC<-PC + k +1, send to 0x152C  
0x1F98:		rjmp -0x86A	 ;Relative Jump   PC<-PC + k +1, send to 0x1730  
0x1F9A:		rjmp -0x668	 ;Relative Jump   PC<-PC + k +1, send to 0x1934  
0x1F9C:		rjmp -0x466	 ;Relative Jump   PC<-PC + k +1, send to 0x1B38  
0x1F9E:		rjmp -0x264	 ;Relative Jump   PC<-PC + k +1, send to 0x1D3C  
0x1FA0:		rjmp -0x62	 ;Relative Jump   PC<-PC + k +1, send to 0x1F40  
0x1FA2:		rcall +0x416	 ;Relative Subroutine Call, me goto: 0x2144  
0x1FA4:		rcall +0x930	 ;Relative Subroutine Call, me goto: 0x2348  
0x1FA6:		rcall +0x1444	 ;Relative Subroutine Call, me goto: 0x254C  
0x1FA8:		rcall +0x1958	 ;Relative Subroutine Call, me goto: 0x2750  
0x1FAA:		rcall +0x2472	 ;Relative Subroutine Call, me goto: 0x2954  
0x1FAC:		rcall +0x2986	 ;Relative Subroutine Call, me goto: 0x2B58  
0x1FAE:		rcall +0x3500	 ;Relative Subroutine Call, me goto: 0x2D5C  
0x1FB0:		rcall +0x4014	 ;Relative Subroutine Call, me goto: 0x2F60  
0x1FB2:		rcall -0x3664	 ;Relative Subroutine Call, me goto: 0x1164  
0x1FB4:		rcall -0x3150	 ;Relative Subroutine Call, me goto: 0x1368  
0x1FB6:		rcall -0x2636	 ;Relative Subroutine Call, me goto: 0x156C  
0x1FB8:		rcall -0x2122	 ;Relative Subroutine Call, me goto: 0x1770  
0x1FBA:		rcall -0x1608	 ;Relative Subroutine Call, me goto: 0x1974  
0x1FBC:		rcall -0x1094	 ;Relative Subroutine Call, me goto: 0x1B78  
0x1FBE:		rcall -0x580	 ;Relative Subroutine Call, me goto: 0x1D7C  
0x1FC0:		rcall -0x66	 ;Relative Subroutine Call, me goto: 0x1F80  
0x1FC2:		ldi r14, r0	 ;Load Immediate  Rd <-K
0x1FC4:		ldi r30, r1	 ;Load Immediate  Rd <-K
0x1FC6:		ldi r14, r18	 ;Load Immediate  Rd <-K
0x1FC8:		ldi r30, r19	 ;Load Immediate  Rd <-K
0x1FCA:		ldi r14, r4	 ;Load Immediate  Rd <-K
0x1FCC:		ldi r30, r5	 ;Load Immediate  Rd <-K
0x1FCE:		ldi r14, r22	 ;Load Immediate  Rd <-K
0x1FD0:		ldi r30, r23	 ;Load Immediate  Rd <-K
0x1FD2:		ldi r14, r8	 ;Load Immediate  Rd <-K
0x1FD4:		ldi r30, r9	 ;Load Immediate  Rd <-K
0x1FD6:		ldi r14, r26	 ;Load Immediate  Rd <-K
0x1FD8:		ldi r30, r27	 ;Load Immediate  Rd <-K
0x1FDA:		ldi r14, r12	 ;Load Immediate  Rd <-K
0x1FDC:		ldi r30, r13	 ;Load Immediate  Rd <-K
0x1FDE:		ldi r14, r30	 ;Load Immediate  Rd <-K
0x1FE0:		ser r30		 ;Set Register    Rd<-$FF
0x1FE2:		brbs  0x0, +0x3C	 ;Branch if Status Flag Set => if (SREG(C)=1) then goto 0x2020
Equivalent: 	brcs +0x3C ;Branch if Carry Set if(C=1)thenPC<-PC + k+1
0x1FE4:		brbs  0x1, +0x7C	 ;Branch if Status Flag Set => if (SREG(Z)=1) then goto 0x2062
Equivalent: 	breq +0x7C ;Branch if Equal if(Z=1)thenPC<-PC + k + 1
0x1FE6:		brbs  0x2, -0x44	 ;Branch if Status Flag Set => if (SREG(N)=1) then goto 0x1FA4
Equivalent: 	brmi -0x44 ;Branch if Minus if (N = 1) then PC <- PC + k + 1
0x1FE8:		brbs  0x3, -0x4	 ;Branch if Status Flag Set => if (SREG(V)=1) then goto 0x1FE6
Equivalent: 	brvs -0x4 ;Branch If Overflow Flag Is Set  if (V = 1) then PC <- PC + k + 1
0x1FEA:		brbc  0x4, +0x3C	 ;Branch if Status Flag Cleared => if (SREG(S)=0) then goto 0x2028
Equivalent: 	brlt +0x3C ;Branch if Less Than Zero, Signed    if (N ffi V= 1) then PC <- PC + k + 1
0x1FEC:		brbc  0x5, +0x7C	 ;Branch if Status Flag Cleared => if (SREG(H)=0) then goto 0x206A
Equivalent: 	brhs +0x7C ;Branch if Half Carry Flag Set   if(H = 1)thenPC<-PC + k+1
0x1FEE:		brbc  0x6, -0x44	 ;Branch if Status Flag Cleared => if (SREG(T)=0) then goto 0x1FAC
Equivalent: 	brts -0x44 ;Branch if T Flag Set    if(T=1)thenPC<-PC + k +1
0x1FF0:		brbc  0x7, -0x4	 ;Branch if Status Flag Cleared => if (SREG(I)=0) then goto 0x1FEE
Equivalent: 	brie -0x4 ;Branch if Interrupt Enabled if(l = 1)thenPC<-PC + k+1
0x1FF2:		;Unknown command CODE: 0xF8F8
0x1FF4:		;Unknown command CODE: 0xF9F9
0x1FF6:		;Unknown command CODE: 0xFAFA
0x1FF8:		;Unknown command CODE: 0xFBFB
0x1FFA:		;Unknown command CODE: 0xFCFC
0x1FFC:		;Unknown command CODE: 0xFDFD
0x1FFE:		;Unknown command CODE: 0xFEFE
0x2000:		;Unknown command CODE: 0xFFFF
